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Thankyou Sir!, You seem to be expert in silvaco can you also please tell me whats the fastest way to learn silvaco? As there are numerous documents/sites on the topic but none seem to help a beginner like me! So as you know much about the software can you tell which file/doc you think you must...
Hi,
I've been assigned to design a non conventional FET (FINFET,Quadfet etc.) in silvaco and then somehow extract and feed the generated device parameters into Cadence for making a single stage amplifier. I wanted to ask if it is possible?? and if yes then how it could be done??
Thank you very...
Thankyou sir for your timely reply!
I was also thinking to generate a small pulse using the load as you did but wont the logic assign load_pulse = ~load & load_dly; give a zero output while simulating in modelsim/Xilinx? Also the frequency of the PLL is not fixed so I dont think it is possible...
Hi, I am designing a jitter bounded DPLL in verilog for which I need a T flip-flop (for a down counter) which can toggle output on positive edge and load data asynchronously on negative edge. I wrote the code but it is not working as needed. Code is :-
module tff_async_load (
data , // Data...
HI,
I am new to system verilog and was trying to simulate the following simple program but am not able to understand how the output is beign generated:
module test ();
initial
begin
byte XYZ[4][7];
foreach(XYZ[i,j])
XYZ[i][j]=i*100+j;
foreach (XYZ[i])
begin...
Hi rajni, have you already made the SNM curve for hold?? if yes ,just apply the concept of read i.e. apply initial condition in both the lines by setting them high using .IC command format being .IC V(x)=XXv where x is node and xx is voltage to which you have to charge your bit lines and then...
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