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Recent content by matthew_wang

  1. M

    question about linux taskes dispatch

    linux dispatch task Hi All I have an linux machine with multiple CPU, I want to dispatch task according to CPU loading, if one of them is not busy, then dispatch a task. Does anyone known which tool or script can do this job? Thanks
  2. M

    verilog-a question (about system task $fopen)

    $fopen in verilog In the verilog 1995, there is no append mode, but in the verilog 2001, they do add some open file mode to $fopen task you can use t = $fopne( filename, "a" ); or t = $fopen( filename, "a+" );
  3. M

    about conditional execution

    Dear all: Have someone done the ARM asm coding? I want to know in what case, this conditional executive will be used? How many cycles will be save when you use conditional executive instruction? And it seems a little confuse that the flag will be changed every cycle, if the conditional...
  4. M

    Pipelining Techniques

    This is a very large range question, it is very difficult to give out an answer in just few word. Currently, the pipeline structures from some classic implementation is a hybrid of RISC/CISC/VLIW, supperscaler, I think you can start from some papers on these pipeline and instruction set
  5. M

    about conditional execution

    Hi, all about the conditional execution, I am do a research about this topic, but it seems that this way can only separate the "if..else.." to sequencial program, and maybe this can't save much time. And what architectecture is for "conditional execution" Or you can recommend some materials...
  6. M

    Looking for information about rmvb codec

    Hello everyone I want to know some detail about rmvb codec, what difference form other codec, like VC-1, H.series, MPEG-...? Could you give me some reference document or links? Thanks
  7. M

    Problem with code for submodule which generates clocks for other submodules

    synthesize problem Hi, When you run simulation, Is outdata[0] bit always zero?
  8. M

    systolic Vs General Array

    I think systolic does not only mean faster and bigger, the PE array structure also can be done very fast.
  9. M

    synopsys DC synthesis problem

    assign dc synopsys Please go to synopsys, solvenet.com, I think you can get solution quickly.
  10. M

    systolic Vs General Array

    I think this classic book for vector arrray processor has been updated, but the pointes needed are too much for me, I am poor. fast or slow, is not only point, for systolic , it is more regular and esay for backend, but others maybe cost more than systolic. The speed of other array can be...
  11. M

    systolic Vs General Array

    how about the cost of two kinds of design?
  12. M

    systolic Vs General Array

    What is the advantage of the systolic array compared with general PE array? Could someone do me a favor to recommend some classic materials about systolic design? Thanks
  13. M

    Looking for watermarking algorithm using MATLAB

    watermarking which field does your watermark be used?
  14. M

    Guidelines for RTL and Behavioural

    RTL and behavioral coding is from different design view. The latter focuses on module, it does not concern the internal details.
  15. M

    fail in post-layout simulation

    please use lower frenquency firstly, if works, then setup time violation, but I think you need to do some STA again.
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