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Thank you for your answer.
Then if we are very interested in frequency between 0 and F_carrier, why do we only look at frequencies higher than F_carrier (cf the figure in my post) ?
Best
Hello everyone,
I am designing my first PLL.
The input clock will be around 32.786 kHz and the VCO's free running frequency is at 32.786 kHz. I am currently trying to estimate the VCO's and input clock's phase noise to set the optimized bandwidth and then get the minimum output jitter.
I...
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