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Recent content by matin-kh

  1. M

    Issues with AM Modulation Using NI 9263 and NI 9239 Modules

    Hello everyone, I am utilizing an NI 9263 analog output to generate a sine voltage with a frequency of 1 kHz and a peak voltage of 10 V. The intention is to use this signal as a carrier in a system for amplitude modulation (AM). The message signal is in the millivolt range, and I am acquiring...
  2. M

    [SOLVED] Programmable waveform generator

    Hi, I need a programmable waveform generator to use in my circuit, I need to generate square wave and sine wave and also sum of several (up to 5) sine waves. It should be adjustable and I need these specifications: Frequency range: 20Hz-20KHz Amlitude range: 1mv-2v I found some ICs as like as...
  3. M

    Measuring ECG and at the same time the mismatch impedance

    Hi, I have a question regarding the below circuit. The circuit below is for measuring ECG and at the same time it wants to measure the mismatched impedance of the electrodes connected to the body by adding a common mode signal "Vadd" in the positive input of the DRL opamp OPDRL. In the related...
  4. M

    Adaptive filters fundamental

    Hi, I am looking for a good reference book, tutorial or ect... for understanding adaptive filters which I want to use it in eliminating motion artifacts from ECG signals. Could you please help me regarding it?
  5. M

    Understand the fillter function throughout the solved differential equations

    Sorry I forgot to say that in equation 1 we assumed Vinj is zero so consider the next equations without Vinj. Let me explain a bit about this system it is a contactless ECG sensor which measure the ECG from the body without any contact which it means a capacitor is formed between the body and...
  6. M

    Understand the fillter function throughout the solved differential equations

    Hi, The aim is measuring Vecg through a capacitance sensor in the pictures below and the equations are written down, in the paper related to these pictures says: "The first term on the right hand side of Eq. 1, s(t), shows that the signal of interest Vecg(t) is filtered by the system and that...
  7. M

    [SOLVED] electrode-skin impedance mismatch

    Hi, there is a term in measuring biopotentials,"electrode-skin impedance mismatch". I cannot understand its meaning. Is there anyone who can explain it for me? Thanks
  8. M

    FGPA programmed successfully but it doesn't work correctly

    Re: fpga programmed successfully but it doesn't work correctley Hi I'm sure I load the correct file. it doesn't work yet, I checked all the things over and over again but I could not understand what is wrong :( it programmed successfully but when I want to check the GPIOs by voltmeter the...
  9. M

    FGPA programmed successfully but it doesn't work correctly

    fpga programmed successfully but it doesn't work correctley Hi every one, I wanted to check the FPGA(spartan 6(xc6slx150)) on the board so I wrote a very simple code as below: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity test is Port ( out_put : out STD_LOGIC_VECTOR (9 downto 0) )...
  10. M

    question about use two CMT in different primitives in spartan 6

    thank you very much in advance for your reply. it makes no difference for me to use DCM_CLKGEN or DCP_SP if I use DCM_SP it is ok to define it's output as a signal and then run another clocking wizard and use this signal as the input of the DCM_SP? like this: library IEEE; use...
  11. M

    question about use two CMT in different primitives in spartan 6

    hi every one, I have a spartan 6(XC6SLX150) which it's input clock is a differential pair and it's value is 12.8Mhz, I understood which I couldn't use pll_base because it's minimum input frequency should be 19MHz. If I want to use Pll_base can I produce a frequency higher than 12.8 MHz with...
  12. M

    question about CMT of the spartan 6

    Hi every one, I underestood that the model of spartan 6 which I'm working on it(XC6SLX150) has 6 CMT so it has 6 PLL and 12 DCM. I have two question now: 1- I run clocking wizard on my ISE and there I understood there are three modes which I can select *DCM_SP--->which contains to mode, DCM to...
  13. M

    question about gclk and program the fpga through jtag

    Hi everyone I have three question: 1- when I want to program the fpga(spartan 6) doesn't need to enter an external clock to fpga?I mean jtag will enter the clock to fpga and we don't have any external clock am I right? and does need to change the mode pins of FPGA to the slave mode? 2-if I want...
  14. M

    use rising edge and falling edge of the clock in vhdl

    hi every one, I want to use both edge of the clock but I have problem to develop it. I write a simple code for the process like below to check it: process(x(3),res) begin if(res='1') then a<='0'; b<='0'; elsif (x(3)'event and x(3)='1') then a<='1'; b<='0'; elsif (x(3)'event and...
  15. M

    use C to program FPGA

    thank you all. I have learnt VHDL and I can program FPGA in VHDL but my boss has forced me to program it in C because he believes it is easier I told him that I know VHDL and it is easier for me to to use VHDL but he is insisting on his own words!! :)، so I started searching about C language for...

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