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Recent content by mathi

  1. M

    Why PMOS for pull up and NMOS for pull down?

    Say you have your Vdd connected to the drain of the nmos and the output is taken at the source. When apply Vdd to the input terminal and if the gate-source voltage Vgs > vth, then you have an inverted channel and Vds > 0 causes current to flow to the source charging it up and pulling the source...
  2. M

    synopsys design compiler

    Thanks Atre, I got it work.
  3. M

    synopsys design compiler

    force design compiler Hi all, I want to know if there is a way of preventing design compiler from removing used pins when writing the gate-level netlist? My library has flip-flops with inputs and outputs declared as follows DFF(CLK, D, Q, QN). When I save the netlist using desing compiler...
  4. M

    Cadence First Encounter & flip flops

    I am using tsmc 0.18. Is there a way I can force encounter to include the Q bar as well? I don't want to change the code cause its 1000s of lines.
  5. M

    Cadence First Encounter & flip flops

    HI all, I trying to do gate-level simulation after place and route. I saved the netlist from encounter but when i try to simulate it, it complains about too few arguments for flip flop instances, missing QN (complementary Q). I checked the library file and QN is declared there. Is there a...
  6. M

    The difference between VDD core and VDD ring

    vdd core can someone tell me the difference between VDD core and VDD ring?
  7. M

    simvision and SDF file

    Hi all, I am trying to do post-layout simulation using simvision. I have extracted the SDF file from encounter. Can someone tell me how i can include the SDF file in the simulation. Thanks.
  8. M

    biasing differential amplifier

    Re: biasing analog IC Thanks for your explaination, really helped.
  9. M

    biasing differential amplifier

    Re: biasing analog IC Thanks for your tips guys. You can only consider the transistors individually only if you neglect channel length modulation. In sub-micron devices you have to consider the channel length modulation, which means you have to consider both transistors at the same time in the...
  10. M

    biasing differential amplifier

    Re: biasing analog IC Thank you all for responding, do you think being able to hand calculate biasing points is critical. To get a good value you would have to take into consideration all the transistors in the branch. For a simple common source amplifier with a current source (mos in...
  11. M

    post-layout simulation

    Thank you all for responding, does anyone know or have a step by step tutorial using cadence tools that i can follow to do post-layout simulation.
  12. M

    post-layout simulation

    Thanks for replying, but can you tell me exactly what tool i am suppose to use once i have extracted the layout with parasitics.
  13. M

    biasing differential amplifier

    biasing analog IC Hi all, where can i learn how to bias analog MOSFET ICs? I know all the conditions but i have trouble calculating by hand the of values of the bias voltages and sizes. Is there a good book or website or anything that i can use to learn to calculate these values? I have...
  14. M

    post-layout simulation

    Hi all, How do you do post-layout simulation of a digital system that has been layed out using encounter and imported into Cadence Virtuoso? thanks.
  15. M

    Simulating tunneling and electron injection usin cadence ADE

    Hi, I am looking for a way to simulate the effects of hot channel injection and electron tunneling, these effects allow current flow through the oxide dielectric. Any suggestions or guidence would be helpful. thanks.
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