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If I choose charge pump structure with a input voltage about 5V, the effiency will be very low and the Iq of my chip can be several mA large; And if I use boost, because the load is so light, so I also can not get a good effiency?
Can somebody provide a solution on this ? Need your help.
input sensitivity +4db and -10db
hi, yubingz
the result of the eqution that you give is -147dBm, not -109dBm.
This question is in th e first page of chapter6 in RF electronics(Razavi).
what's the problem?
thx!!!
input sensitivity
When i read about input sensitivity in Section2.4 of RF microelctronics(RAZAVI),
i am confused about input sensitivity caculation.
If a SNR of 8dB in a bandwidth of 200kHz is required, and the total NF is 4dB, so how to caculate the input sensitivity is about -109dBm?
Re: ABOUT DC-DC
hi,
there are two general ways using this chipAS1340 as the datasheet poses, split supply and not.
That Vin in your application is 7.2V, which is above 5.5V ,it need to split supply.In the datasheet,there is a graph showing the relation between Iout and Vin,hope it be useful.
hi,
Mismatch is a result of both layout and manufacture in foundry, it's quite different according to different layout methods and foundries. So, i think it's good to investigate the total device mismatch of a foundry and to do most of the job to optimize the layout.
Masteric
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