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When you say it suffers when driving a 20 MHz signal. What do you mean? Are the edges too slow? Doesn't it even reach full amplitude?
A common mistake I see is that people expect the rise and fall time to be close to non existing but you should consider what you need in your application.
Since you use Virtuoso you can check a porting script done by Andrew Beckett.
You have to define the device mapping and also be careful about callbacks.
But bottom line is that it is a very crude porting, you can't really draw any conclusions about the process performance or be sure that the...
I think one important aspect, perhaps not as important as the other mentioned but still, is that the gm/Id method is more direct. Both gm and Id directly describe something in the circuit compared to Vov which in itself doesn't really say much.
The two mirrors does not have the same ratio 61 for the first one and 60 for the second one. Also the parasitic capacitance is different between the two.
Also the operating point might be different. What kind of distortion do you see? Run a DC sweep where you sweep the input voltage and a...
You don't give enough information for an actual answer but I can try and guess!
With a 1:64 ratio you probably end up with either a large Veff or a large transistor. A large Veff results in distortions earlier.
But without knowing sizes, type of distortion, operating points, some...
As much separation as you get in schematic, infinit, is not possible.
What you can do is to separate them in a few different ways.
If deep nwells are available you can use them or otherwise make low ohmic guard rings that pick up substrate noise so it does not propagate to the analog part...
Okay then I understand where you got it from. The unit in this case is dBV, when you take 20log10(Volt) your unit is not dB but dBV.
But I would stop earlier in the equation, you have A_noise, just find A_signal and you're done.
Best way is probably to refer the noise back to the input and compare with the expected input signal.
Since you have a certain gain your output signal depends on the input signal amplitude and your SNR will only be valid for a certain input/output amplitude.
No need to run a transient. Run...
The masw2000 datasheet specifies a Ton and Toff of 3 ns from 50% of the control signal to 10 or 90% of RF. This means, I assume, it takes 6 ns to switch over even with an infinitely fast driver.
Also, when you say the inverter is to slow and you want it to output a -5 V signal from a FPGA...
The differential input signal is the difference between the two inputs which in your case is 0. You only change the common mode level of the 0 amplitude input signal.
Set two voltage sources to, for example, 0.5 V AC amplitude and whatever DC level you have. One should have 0 degrees phase and...
Some ideas:
Reduce swing
Increase supply
All kind of negative feedback (source degeneration for example)
Filtering input
Without knowing your circuit and your requirements it's hard to give specific pointers.
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