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Recent content by Markie

  1. M

    help: suggestion for LED driver low offset

    I am designing the four channel led driver with charge pump, I need four channels are perfect matching with the goal current and the output resistor is low, so offset cancell amplifier is needed. But I don't know the auto zero and chopper amplifier which one is suit for my necessary. Due to my...
  2. M

    IC5141 problem as it can't find shared libraries

    Re: ic5141 problem same problem. I install the IC5033 in SUSE 10.2
  3. M

    Problem installing IC_5.0.32 on suse32_10.1

    I have the same problem in cadence installing. Anyone can help? Whether the only method is to downgrad gcc to 2.3.2?
  4. M

    A question about load transcient of self-biased folded casco

    Do you have read the paper "A Self-Biased High Performance Folded Cascode CMOS Op-Amp"? which can search in google. I don't really understand equation(10) and(11). If you know it, can you explain them clearly? They are about Transcient load derive.
  5. M

    OTA PSRR based on Steyaert

    Hi, If any of you have read the following paper, please help. Power supply rejection ratio in operational transconductance amplifiers Willy Sansen and M S J Steyaert IEEE transaction on circuit and systems Sept 1990 I anxious about How to hand calculate PSR in TableI. And I really want...
  6. M

    How to properly do AC open loop LDO simulation?

    ac analysis of ldo I also confused it, sometimes, I use the AC source with ac=1V to break the loop. sometime, I use the resistor with AC=1G , and a cap=1F . and sometime, I use the ind=1G and a cap =1F. the only diff thing I thought is the phase of it different. But offten, the gain plot...
  7. M

    what's the droop in LDO

    In some datasheet, there is the droop pic of Vout trans with Iload. who can tell me what the cause of droop is? I think that the droop is come from gold bond wire of Vout. When load transient is under test, shall we add some resistors to topo of test?
  8. M

    about the LDO regulator PSRR

    I want to know what the goal to add ESR in simulation and what ESR will perfect? We use a version of LDO "117" in our design, but if we don't add the cap on output term, it will wave. If we don't want to add the input and output capacitor, we should use the chip of what PSRR? does this...
  9. M

    about offset cancelling in comparator

    hi, I have know a good network that "h**p://www.edacafe.com" then you can seach for chopper, a PHD thesis will give you a lot of knowledge about it. Or IEEE will help you. I am also interested with chopper. ^$^
  10. M

    Higher and lower bandwidth in 4 stage amplifier

    Re: bandwidth If you want to exactly understand about it. I suggest you to use open-circuit time constants method to analyze your topo. then you will see what serversly effect your bandwidth. If you don't know the "open circuit time constant", you can see "tomath lee".
  11. M

    SCts methods calculate the cascode amplifier

    I read the lee's Rf circuits book, I am confused. In ch7, hwo he can say that using short circuit time constants methods, what happens to the low-frequency gain if we take the following fig's Cin and Ce out of the circuit?
  12. M

    question about the stability of the system

    if a RHP is exist, to phase margin, is it equal to the zero phenomenon ?
  13. M

    question about the stability of the system

    I don't quite understand your meaning. I think that the stability is consideraly with the Phase Margin, that is, commonly it's the distance between polar P1 and P2. You say that if RHP is exist, then the circuit oscilate. Yes, it will oscillate eventually at its native frequence, nor related...
  14. M

    About the p-channel input stage? (question about martin's)

    Re: About the p-channel input stage? (question about martin' Sorry for disturbing you! You say that because gm/Id ratio is worth for PMOS, the circuit will increase power consumption. Due to my knowledge, gm/Id only relates to the over-voltage! Can you explain it clearly? thanks

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