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I have a top level verilog file, which declares all the inputs, outputs, regs and wires for several sub-files.
FetchStage1 fs1( .stall_i(instBufferFull | ctiQueueFull),
.clk(clock),
.reset(reset),
.lastPC)
I get the following error while compiling:dot...
Hi,
I have a piece of Verilog code in an always block (with a posedge clock in the sensitivity list) that I am able to simulate but not synthesize using Synopsys Design Vision:
ctrlList.sram[addr1] <= 0;
All statements in the always block are non blocking. Other accesses to the sram module...
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