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Recent content by manalog

  1. M

    desing differential op-amp

    will your diff-ckt really works as an Op-amp with positive feedback!!!!? don't you think that your output will be saturated in voltage domain. or in other words, for input diff voltage the positive feedback will drive the output stage to any of the supply rails ( VDD or VSS). so what do you...
  2. M

    About Bandgap Reference (BGR)...????

    Thanks for reply, I will study that doc. But i didn't understand this: In case of BJT, the 'B' will vary with PVT corners and that will result in a VREF variation. Because more B -> less Ib -> more Ic, And less B -> more Ib -> less Ic. That means if B varies the Ic will vary, which will vary...
  3. M

    About Bandgap Reference (BGR)...????

    Dear All, I am designing a BGR for LVDS TX for supply(VDD)=1.8V. I am using Conventional BGR circuit, which is composed of CMOS op-amp, BJT & Resistors ( as shown in following fig.). The circuit is working properly, means I got the good curve for VREF vs TEMP. VREF(@minTemp)=1.1855V ...
  4. M

    [SOLVED] Why -ve terminal of supply need to connect to ground????

    Take an example of simple calculator: - Calculator needs only one battery to run. ( Battery with one "+ve" & one "-ve" terminal). - Calculator's body is usually made up of an insulator. Does it mean the calculator doesn't need ground connection??? BUT, when I am doing a simulation with one MOS...
  5. M

    How to simulate an Opamp for input common mode range (ICMR)

    First definition means DC analysis!!! For two-stage op-amp (nearly 8 mos devices) its fine, but what if its multistage opamp ? this dc simulation method doesn't look practical. Isn't it?
  6. M

    How to simulate an Opamp for input common mode range (ICMR)

    Hello all, Today I have simulated an Two-stage opamp to find out its ICMR. To find out ICMR i gave dc input @ VIN+, & VIN- is connected to VOUT. And plotted VOUT after DC simulation. As nmos differential pair is used at input, i was expecting the VOUT to be linear from V1 to VDD ( where V1 >...

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