Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi all,
I tried to model the circuit which required the repeat calculation such as
Resistor in out R = A*10
Where A is calculated from the other equations such as
A = V(in,out)+step*I(Resistor)
When the parameter A is updated, the resistance will change and parameter A will update again...
Hi all,
I have some questions about HSPICE,
Since I wondered that is it possible that I count and reset the time that voltage across element ?
For example,
I generated that subcircuit that resistance varied with time
Thank you for your help
Hi Milad-D,
I understand your point, but the thing is at the first simulation which gate voltage is 1V, voltage at node S is 1V.
To make it more simple, I change the gate voltage to
Vin Gb 0 DC Vd
The result is voltage at node S is 1V.
Thank you for your answer erikl
I am not really understand your answer
However, I attach picture of my model that I simulated.
Since I would like to check that PMOS could pass the VDD or not, this circuit is generated. By check the voltage at node S, when GB = 1V (or Vd). In my view, when GB...
Hi all,
I tried to use HSPICE to simulate the regular PMOS circuit,
However, my problem is, why does source voltage is equal to 1V when gate voltage is equal to 1V.
The following is my code
Thank you so much for your help
Best
PJ
Test
.include 'PMOS 45nm.txt'
.param Vd = 1V
Vsupply 1 0...
Hi all,
Thank you for your answer,
I used HSPICE to simulate this circuit, by consider at V1 and V2 is Vdd.
Let Vdd = 0.9V
The strange result this voltage at node C is equal to 0.13 something, which I concerned that,
From this circuit, if V1 and V2 is Vdd, the other transistor is on/off ...
Dear All,
I have some question about floating node. As the following picture,
If I set V1 to be Vdd all the time.
and V2 is Vdd at the first period, then set V2 is 0 (Which is close NMOS)
My question is, what is the value of the voltage at node C ?
and if V2 is zero, the other transistor...
In my opinion, (If i am not misunderstood)
Current that you would like to plot is current from Voltage source.
Since current is to flow from positive to negative, by consider current based on voltage source, it's inverse to the regular behavior.
To fix this problem, why don't you add another...
Now I got the answer,
To changed this problem, in my view, the code should be
Gswitch1 11 0 VCR PWL(1) 0 11 -0.00002V,1000Meg 0V,0.01 Max=1000Meg min=0.01
Gswitch2 11 ref VCR PWL(1) 11 ref 0V,1000Meg 0.00002V,0.01 Max=1000Meg min=0.01
Dear all,
I have some questions about switch model in SPICE as the following.
For example,
S1 1 2 3 4 Switch
.model switch sw(Ron=0.01, Roff=1000, Vt=0.001, Vh=0.0001)
1. From the above code, Switch S1 (output is node 1 0) is controlled by node 3 4, am I correct ?
2. What is Ron and Roff ...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.