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Recent content by makanaky

  1. M

    Theoritical limit for MSK Eb/No

    Hello, Can somebody provide the theoritical probability of error relation for MSK and GMSK as I found different ones on different texts Thanks
  2. M

    MSK to OQPSK mapping

    Hi, I know that MSK can be interpreted as OQPSK and vice versa, the only issue I have is to find and prove the bit mapping relation, so that the bits input to MSK modulator (VCO) can be provided to OQPSK modulator (I,Q modulator). The relation I can reach for MSK is : yMSK=...
  3. M

    How to force Synthesis tool use standard cell library MUX for implementing MUXs

    Hi, I am using RTL compiler to synthesize a critical path of MUXs, and the tool implements the MUX using gates (NAND, OR ... etc). I am afraid this may increase the path delay while the std cell library contains MUX cells. Is there a way to instruct the tool to use a std cell MUX instead of gates ?
  4. M

    RTL compiler Synthesis options to optimize timing

    Hi, Are there any techniques that I can use to make RTL compiler achieve better slack for critical path in my design ? I mean synthesis techniques not front end (pipelining and so ) Thanks
  5. M

    Questions in APR using Encounter

    Hi, I am new to APR so please excuse me if my questions seem lame. Should the netlist output from synthesis have VDD/VSS ? Also, Do I have to add Power rings in Encounter to be able to place std cells ? As I do place but nothing appears in the layout . Thanks
  6. M

    Is LEF file mandatory for Place and Route ?

    Hi, I am using SOC encounter for APR for the 1st time. It seems a LEF file is required for Floorplanning, but I cannot find any LEF in the std cell library. So can you please give me any hint ?Is LEF mandatory ?
  7. M

    Fastest method to read/write data into Nexys3 FPGA board

    Hello, I want to ask about the fastest method to read/write data into Nexys3 FPGA board. I use the parallel port method but it's really slow (in the order of 50 bps ). I need communication of at least 10 Mbps . Thanks
  8. M

    RTL compiler insert certain combinational delay

    thanks all for trying to help , I found command called "path_delay -from x -to y " , it modifies the SDC but this is not reflected in SDF , is there any method to view this on simulation ?
  9. M

    RTL compiler insert certain combinational delay

    Hi, Is there a command in RC to insert certain delay between 2 signals ?
  10. M

    Nexys 3 Board problem with reading /writing registers

    Yea I know, its just registers read/write . plus this is the template provided by digilent anyway and its not a functional bug , its a hardware issue that the register cannot be read/written
  11. M

    Nexys 3 Board problem with reading /writing registers

    Its too simple to simulate :)
  12. M

    Nexys 3 Board problem with reading /writing registers

    Have you caught any issue Shaiko ?
  13. M

    Nexys 3 Board problem with reading /writing registers

    This is the top level : ---------------------------------------------------------------------------- -- dig_equalizer.VHD -- Digilent Parallel Interface Module Reference Design ---------------------------------------------------------------------------- -- Author: Gene Apperson --...
  14. M

    Nexys 3 Board problem with reading /writing registers

    Hi Shaiko : Here's my cpp code : It basically reads a file (Read.txt) of integers ranging from -7 to 7 , input these to the FPGA which processes these values, and registers '1' in case of positive value, '0' otherwise. The software then writes theses comparator results to another file...
  15. M

    Nexys 3 Board problem with reading /writing registers

    Hi, I wrote a software that writes data to the FPGA register, and read the processing results. I found that for repetitive read/write, the software fails to read registers anymore (the DpcPutReg function returns -1) I also tried to make this using Adept software, after some (10~30)...
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