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Recent content by Majid_Vatan_Parast

  1. M

    LVS for HSPICE netlist

    Hi everyone I have HSPICE netlist of a circuit and have drawn its layout in Cadence. I want to run LVS for this netlist with Calibre, but do not know how the Calibre set up should be. Can anyone help me with the appropriate set up ? Thanks in advance
  2. M

    [Moved] Comparator offset cancellation

    Hi It is an actual circuitry, I am designing a 2b/c SAR ADC. It is a dynamic comparator with single supply. I want to implement a current mode offset cancellation circuitry. Do I need to perform offset cancellation in every cycle ( every T ) or it is done only once? When offset cancellation...
  3. M

    [Moved] Comparator offset cancellation

    Hello everybody I need to remove the offset of a comparator, but I have problem understanding the timing of offset cancellation and routine operation of the comparator. Can anyone help me please 😭😭 It is urgent Please help me 😥😥
  4. M

    Cadence 6.1.4 on CentOS (***** cadence)

    Hello everybody I have 6.1.4 cadence On CentOS(eslam cadence), but I can not run DRC because I can not set up DRC . Can anyone help me.:-( I uploaded a picture. I can not set up the Runset file path.
  5. M

    Common Mode Feedback Test Circuit

    Vcm is desired output DC voltage and is a fixed voltage .
  6. M

    Common Mode Feedback Test Circuit

    Hi I have designed a capacitive common mode feedback ,but I do not know ho to test if it works or not. Can anyone suggest me a test bench circuit for common mode feedback? Picture below is schematic of my circuit. Thanks in advance
  7. M

    Common Mode Feedback

    Voltage source is VDD=1.8 .Input transistors gate voltage is 0.8v. Vcm is a little bit more than VDD/2(Vcm=930mv).
  8. M

    Common Mode Feedback

    Vcm=930mv , Vb=600mv .I use DC voltage sources to generate them.
  9. M

    Common Mode Feedback

    Vcm is the desired DC voltage of output nodes . Vb is the voltage that must be applied to gate of tail transistor to generate desired tail current .
  10. M

    Common Mode Feedback

    When I change the size of PMOS transistors at the top of the circuit , DC voltage of output nodes changes and CMFB can not tie them to desired voltage , that is why I think CMFB circuit does not work .
  11. M

    Common Mode Feedback

    For simplicity voltages are generated by DC voltage sources , clock phases are generated by a Non-Overlapping clock generator .Schematic of the circuit ,and voltage of output node are shown in the following pictures.
  12. M

    Common Mode Feedback

    My circuit is exactly like that . My picture is shown in the picture .
  13. M

    Common Mode Feedback

    Hello I want to design a capacitive common mode feedback , I have a circuit but it does not work .Can anyone tell me the problem of the circuit ?
  14. M

    MDAC for a Pipelined-SAR ADC

    Hello everybody I want to design a MADC for a Pipeliled-SAR ADC , but I have problems . I have designed a 2-satge Op-Amp that first stage is a Cascode . Op-Amp needs 0.78 V common mode in input to work correctly . when I put it in a capacitive feedback Op-Amp dose not work because capacitors...
  15. M

    [Moved]: Analog to digital converter

    Hello everybody In an ADC, how Vref, input voltage range and voltage supply are related together ?
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