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hello Aryajur,
from reading your comment, my assumption that all transistor have the same size expect m5 is wrong.
if i know what i want my input and output current to be is there a way to determine the size of the transistors and how to get the highest output resistance? or the only way to do...
i understand for a wide swing cascode current mirror the width for the biasing transistor(M5) is .25 size the rest of the transistor. how to determine the value for W/L is for all the transistors and how keep the transistor where the output transistor(M1) is taking from in saturation
gentleman im back with a new algorithm but the same result. i use Kevin testbench, im getting, ---10 NS
Assertion ERROR at 10 NS in design unit TB_NBITCARRYSKIPADDER(RTL) from process /TB_NBITCARRYSKIPADDER/MAIN:
"OOPS! Doesn't add up"
in the waveform nothing show up for the sum and the...
yes i did use the testbench. after running it with the testbench i did not get anything for the ouput. i received U for the output, sum and Cout, undefined. before Kevin sent me the test i already written my own testbench. i wrote the code for the carry skip adder and carrylookahead adder and i...
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity NbitCarrySkipAdder is
generic (N: integer :=20; --number of bits
R: integer := 4; -- the number of blocks
K: integer := 5); --the number of bits in a block
Port (
a,b: in STD_LOGIC_VECTOR (N-1 downto 0);
cin: in STD_LOGIC...
I NEW TO THIS SITE BUT I THINK I GETTING IT. I MAKE SOME CHANGES ON MY CODE BUT IM STILL GETTING THE SAME ERROR SHOWN BELOW. I WROTE EXACTLY THE SAME FOR LOOP FOR A RIPPLE CARRY ADDER AND IT WORK. I THINK I NEED TO CHANGE C(1) TO C(0) SO AT THE END OF THE FOR LOOP THE CARRY OUT WOULD EQUAL TO...
sorry about that i try to be more specify, im new to vhdl
in my first for loop im trying to implement the propagation for 1 block: propagation for 1bit fulladder is p= a or b; im trying to implement 4 blocks of 5bits fulladder so propagation for the blocks would equal to (p(1st_block= p(0) and...
its not calculate the blocks its compiling but not doing what it suppose to do
can u check this website and tell me if im doing it wrong please
**broken link removed**
-----------------------------------------------------------------------------------------------------------------------------...
thats what im trying to do but its not working
can u show me how to get the first 1
G(0) := a(0) and b(0);
P(0) := a(0) or b(0);
C(1) := G(0) or (P(0) and cin);
for i in 1 to R-1 loop
G(i) := a(i) and b(i);
P(i) := a(i) or b(i);
C(i+1) := G(i) or(P(i) and C(i));
end loop;
can anybody help me with a vhdl code. i trying to write a code for a carry skip adder. i dont know how to use index to implement the block for n bit. i can do it for like 20 bit but not for n bit.
for example p(0)= a(0) or b(0); for 1st fulladder in the block. the block consist of 5 fulladder...
i would like to know the factors that limit the amplifier common mode input range and the output range?
if both ac input are zero why the common mode gain is not zero?
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