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we require general library, to map RTL to gates
delay optimization
setup are resolved by optimizing the path and hold are not touched
refer to manual
learn verilog and synthesis
if you donot want to loose the data from fast clock to slow clock we need to meet timing in most strict case.
with above example if you expand clock for some cycles, the lauch will be at x and capture wil be at x+5 so you need to meet timing for 5 ns
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