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Recent content by mahshidkardan

  1. M

    Would any one introduce me a proper structure for SAR ADC comparator differential ?

    I am designing a low power 100MHz SAR ADC ; but I can not find an accurate differential dynamic comparator for it. Non of the recently published structures work good. Would any one introduce me a proper structure? Thanks
  2. M

    How to find the wireless channel propagation from in-field measurements

    I have collected the received signal strength in dBm in a range within -25 to -110, which is transmitted by a GSM base station with a channel scanner. I want to find out the channel fading based on these signal measurements. The steps that I take into account are as follows: adding the path...
  3. M

    Pipeline ADC transmission gate

    Hi there, I an designing 10-bit pipeline ADC in HSPICe. It works good with ideal switches. However, when I replace the switches with the ideal one, face the following error: **error** internal timestep too small in transient analysis Does any one knows about the reason? Please kindly let me...
  4. M

    Do you know about TSV sizing?

    Hi, I am trying to model TSV in HFSS. I have no idea about TSV sizing in different technologies. Do you know any reference or document including the size of the TSVs in different CMOS technologies(especially 180n and 65n)? Thank you in advance
  5. M

    [moved] 3D technology parameter sizing (TSV and micro bump min/max sizing)

    Hi, Would you please let me know if you have any document which shows TSV and micro bump sizing for different companies in different CMOS-technology IC design? Thanks in advance
  6. M

    Clk synchronization in Pipeline ADC

    Thank you for your note. Actually I know how I can simulate it. But I can not find any reference or publication about how the layout distances can affect the clk synchronization on Pipeline ADC and if there is any solution or arrangement for it. Do you know any related document?
  7. M

    Clk synchronization in Pipeline ADC

    Hi, I have designed a 10-bit pipeline ADC and now I am trying to arrange gain stages around the clk generator(on the layout) in a way that the stages which should be synchronized, receive the clk at the same time. I do not know how much latency causes the distance between clk and gain stages on...
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