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Recent content by Mahrous

  1. M

    FPGA and VHDL/Verilog for Begineers

    have you tried burning any thing on it ? or not yet ! ?
  2. M

    FPGA and VHDL/Verilog for Begineers

    you may do some small projects at first to do specific function like the 7-segment decoders and so try implementing different "ic's" functions if u r completely new , .. if u r ahead of this i suggest you start by exploring a small easy processor architecture and implement it , it really helps...
  3. M

    [SOLVED] Problem including *.h file in Xilinx ISE

    try typing the full path i.e ( "mydolde\myproject\headers\sys.h")
  4. M

    Problem in pin assignments

    why not copy the signal in verilog and then add both original and copied in pin assignment like.. wire LED,GPIO; assign LED = O; assign GPIO = O;
  5. M

    multiple driver can drive one signal

    if you are using xilinx tools you may look at the " ODDR2" HDL macro , it has 1 output , 2 inputs , 2 clocks output is changed on both edges , on clk1 rise in1 is the output , on clk2 rise , in2 is the output and i think you may write your code using multiplexers
  6. M

    [SOLVED] SPI slave clock problem on fpga

    i found the problem ! which is very damn elementary ! ...no common ground for the two boards ! . , connected the ground now it works fine . thanks for all of your efforts
  7. M

    [SOLVED] SPI slave clock problem on fpga

    can i use BUF_TYPE to assing BUFG to SCLK ,and dont' use the internal CLK ?
  8. M

    [SOLVED] SPI slave clock problem on fpga

    here are the pics , sorry for troubling you . i will try to register SCLKr as you said .
  9. M

    [SOLVED] SPI slave clock problem on fpga

    that's a missing edge on the right ,the spi clock is "1/16" MHZ , the internal clock is 27Mhz , some other times when i change very little in the design , like adding a counter for the received bits and put the receiving buffer in the sending buffer "dataBUF2 <= dataBUF" , i monitor the clock to...
  10. M

    [SOLVED] SPI slave clock problem on fpga

    i did visualize the SCLK_IBUF signal in chipsocope and it's some times noisy or missing some edges , but SCLK_rising, SCLK_falling always follow SCLK and is as expected depending on SCLK. if it's a hardware problem what could it be? and would you please mention what fpga text book are you...
  11. M

    [SOLVED] SPI slave clock problem on fpga

    do you mean that i make the process @posedge SCLK instead ? . what i know , is that this is not possible in fpga design , it's synthesis-able of course , but when implementing i receive an error . about receiving an output , thats not the problem , when the clock is read right the data is...
  12. M

    [SOLVED] SPI slave clock problem on fpga

    the speed of the SPI clock is 2 MHz , i checked the voltage level of the outputs from the master , a 1 is 3.3V , a 0 is ~ 0 , which is acceptable as the the levels in the fpga for "1" is 2-4.1 volts ,and a 0 is between -0.5,0.8 volts . i mentioned the internal clock , as it should be faster...
  13. M

    [SOLVED] SPI slave clock problem on fpga

    i have a spartan6 -SP605- fpga board , wrote SPI slave module on it , the problem is the clock from the master is not always read correctly , i managed to implement a debugcore using chipscope and viewed the clock , some times it appears to be perfect other times it has some missing edges ~...
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