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Using Quartus 12, I would like to know why
wait until ((clk'event and clk ='1') or (clk'event and clk ='0'));
won't synthesize to a double edge (raise and fall) flip flop? I get this error
Error (10628): VHDL error at test3.vhd(9): can't implement register for two clock edges combined with a...
It is Quartus.
The RTL diagram is shown below. The FSM is shown as the current_state block. When I double click on the block, I see the FSM and not the flip flops.
So, the map viewer shows the flip flops while not showing combinational logic. On the other hand, the RTL is the reverse.
The following pictures shows part of the result from "technology map viewer (post-mapping)" for a simple FSM design. As I double click on the right LOGIC_CELL_COMB, nothing is shown. I expected to see in the internal structure (gates). Should I do something else?
I would like to know if there are good (preferably open source) VHDL synthesis tools for educational purpose. It doesn't matter if they can not program a device. I know it doesn't look very professional, but Quartus and Vivado (or ISE) are very huge. They easily fill more than 5GB of disk. I...
Lets say in VHDL we have written while assuming that A and B are bit_vector(7 downto 0)
A := B mod 4;
How that is synthesized? Simply mask B with a pattern which is (B AND 000000011). So it is an AND gate.
Now, I want to know how to synthesize (1 mod -4)? The right hand operand is power of 2...
Hi
There is a question about synthesizing mod/rem operators.
X mod N where N is positive:
This can be synthesized by taking the least log2(N) bits of X.
X can be positive of negative (2's complement).
How about negative N numbers?
For example, 1 mod -4 = -3
How this is synthesized?
The same...
Yes, my question is about mapping for sure.
Assume, you are going to map a simple 1-bit full adder to a typical CLB no matter if it is new or old. It is easy to design a two 3-input LUTs for sum and carry. But when it comes to commercial products, some names are changed due to different...
I am looking for an example which shows a simple circuit that is manually placed (mapped) to an FPGA logic block. Assume Xilinx XC4000 which is a simple one and is thought in some textbooks as an example. The explanations only say about the block itself that it is possible to map sequential and...
Well the variable has been initialized. Thing is that, instead of initializing to a constant value, e.g. "000", I wrote a. If I use "000", then the output in the first three cycles become zero.
You said that
, so I thought such thing is valid for signals only and variables should accept such...
OK I understand that. That method is works as I tested.
Apart from the synthesis issues and rules of variable vs. signal, I wonder why using variable doesn't fully work! I know it doesn't make sense, but at least I have to see a working code!
entity test is
port( a: in std_logic_vector(2...
Well assume the input port receives a number (std_logic_vector) and I want to manipulate it. The following doesn't work either
entity test is
port( a: in std_logic_vector(2 downto 0);
clk: in std_logic;
z: out std_logic_vector(2 downto 0));
end;
architecture my of test is
signal...
May I ask why the following code doesn't work?
entity test is
port( a: buffer std_logic_vector(2 downto 0);
clk: in std_logic);
end;
architecture my of test is
begin
process( clk )
begin
if (clk'event and clk = '1') then
a <= a(1 downto 0) &...
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