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Recent content by magesh87ece

  1. M

    anyone tell tool in vhdl?

    what all tool available? 1.simulation=> ? 2.synthesis=> ? 3.static timing analysis => ? and which tool is best and why?
  2. M

    Verilog syntax query!

    answer if (a > X || b>x || c >x) begin Y=X; else Y=P; end here if any one of the a,b,c is greater than x then y=x; else y=p;
  3. M

    Variables in sensitivity list

    use generic statement
  4. M

    Need help to simulate the verilog code given below

    Re: WHY? how many input's temp reg has? for loop will be executed in single clock cycle..............
  5. M

    Case Statement Question???

    library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux is Port ( i : in STD_LOGIC_VECTOR (3 downto 0); s : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC); end mux; architecture Behavioral of mux...
  6. M

    Ideas for project based on FPGA kit

    Re: project idea more application oriented project in vlsi.. i want do in xilinx , fpga kit
  7. M

    Ideas for project based on FPGA kit

    hi all, i want to do a project based on fpga kit........ so give some idea and some good topic....
  8. M

    verilog interview questions

    thanks
  9. M

    verilog interview questions

    hi all, send me some important interview questions in verilog?
  10. M

    what is frequency divider and time divider?

    frequency divider what is frequency divider and time divider?
  11. M

    Which is better for hardware simulation, Verilog or VHDL?

    Re: Verilog or VHDL sent me come important interview question in verilog? what is the difference between intra and inter delay in verilog?
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