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Recent content by mafan88

  1. M

    what's the meaning of the "f"and"r" in t

    what's the meaning of the "f"and"r" in the timing report? when i get the sta timing report ,how can i understand the meaning of the "f" and"r" in the report?
  2. M

    CPU @ RTL Design - Verilog (with complete documentation)

    thank you very much ,i can learn it !
  3. M

    Will DC remove un-used logic when synthesis

    it will remove the unused logic, for i used the formality compare the rtl and netlist ,i find ,the implement have lesser logic,the rest have been optimized!
  4. M

    Interview Questions and Answers

    STA presentation thank you for your sharing!
  5. M

    Interview Questions and Answers

    STA presentation thank you for your sharing
  6. M

    Need VCS manual /User guide/Workshop material

    vcs user manual you can find it at the install directory!there are so many document...

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