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I can simply use a series of if else if statements, like
if (array[0]) begin
index <= 0;
end
else if (array[1]) begin
index <= 1;
end
else if (array[2]) begin
index <= 2;
end
.....
.....
Thss doesn't suit here because the width of this array must be parameterizable, it can be 5, 6...
Hi guys,
Can anyone please help me to design the following circuit
let's say that there's an array of 4 bits (the width of this array should be parameterizable)
I need to find the index of the first occurrence of a '1' in this array when searched from the least significant bit
So
if array is...
I know, this j and found should be initialized in a reset block, or initial block, but that's not the point.
As I know blocking or non blocking statements, both work as non blocking statements when synthesized, this blocking statements only work in sequence in simulation only as per my knowledge...
Hi,
I have a question regarding how verilog for loops work when synthesized
assume this code
reg [7 : 0] array = 2'b10101010;
reg found = 0;
integer j = 0;
integer i;
always @ (posedge clk) begin
for (i = 0; i < 8; i = i + 1) begin
if (array[i]) begin
if (!found) begin...
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