Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
How to set the parameters of 8 bit ideal DAC from ahdl libary of cadence which is require for 6bit ADC . and How to calculate the INL and DNL using ideal_DAC_DNL_8bit from ahdl libary.
How to set the ramp input parameter of ADC . so that it will give correct output.(I am getting the output as attached above )
Actually I am working on VCO based ADC in 180nm technology . I have some doubts related to that topic.
1.I am not getting the correct output after DAC when ramp and...
Need help related to the output after DAC
Can u send me the sample output of DAC when ramp and sine inputs are given to the ADC.
Whatever I have attached the output file , that one is correct or not . Kindly reply
Actually I am working on VCO based ADC in 180nm technology . I have some doubts related to that topic.
1.I am not getting the correct output after DAC when ramp and sine inputs are applied. so kindly let me know how u got the correct output
2. I have set the DAC (Vref=1,Vrise=0...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
