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Recent content by macron

  1. M

    sigma delta simulation question

    hi all, i have design a sigma delta adc. the fft results of both "matlab" and "veriloga" and "veriloga_sw & mos_amp" is fine. if the veriloga sw be changed to cmos-sw, the dc noise peak arise, & independent of fft point number. the 1/R_sw/C_s ~= 6*(2*pi*f_sample). my english is very poor...
  2. M

    sigma-delta modulator snr test

    power domain OK? can you find some tone same as power? cap size OK? thermal noise and flicker noise of OP OK?
  3. M

    How to get a ref bias which higher than supply voltage

    thanks zhlc3 and zhqian: i think charge pump maybe help to get a smoother voltage with little ripple but the biggest problem I encountered is how to implement by using the CMOS of 0.35um, and the ref bias must larger than 12V
  4. M

    how to get a ref bias which higher than supply voltage

    thank u, renwl but the biggest problem I encountered is how to implement by using the CMOS of 0.35um
  5. M

    how to get a ref bias which higher than supply voltage

    In IC, without L, & useing low voltage process how to get this bias?
  6. M

    How to get a ref bias which higher than supply voltage

    in IC, without L, how to get this bias useing low voltage process? thanks
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