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Hi Ranger01,
Good question, you made me think...!!
It is important to run separate tests for stuck-at and transition (atspeed) testing. The two runs will give different test-coverage values, where transition coverage will be 3-4% lower than stuck-at test-coverage. The total list of faults tested...
Hi,
Processes that use chemical-mechanical polishing require limited variation in feature density on metal layers, typically 20 to 80%. Both underutilization (empty or low-routing-density regions) and over utilization (very wide power geometries) affect yields negatively. A region with metal...
Hi,
To understand Fault collapsing and fault equivalence, go through the following two books:
1. Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits (Frontiers in Electronic Testing--agrawal and bushnell)" book.(See sandeep_sggs reply)
2. VLSI Test Principles and...
In DFT, we test for the manufacturing faults. To detect these manufacturing faults there are different fault models that based on algorithms determine the various faults that can arise when the chip is gets fabricated in the fabrication labs. stuck-at fault models and transition fault model are...
JTAG or Joint Test Action Group is a IEEE 1149.1 architecture for testing VLSI chips. It provides a mechanism for controlling the pins of the device under test (DUT) and also monitoring the outputs.
VLSI Test Principles and Architecture is one of the books that provides a good idea about what...
In semiconductor industry, DFT stands for Design For Testability. It is a step in the VLSI design Flow. By using the DFT methodology the chip is tested for manufacturing faults (not functional faults, which are taken care by verification engineers). Manufacturing faults include stuck-at 0...
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