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Recent content by lyko

  1. L

    How to generate the analog models for SOC verification?

    When the analog design finished, how to generate the "real" model(which means that the models include the real connection pins to the digital, not only arithmetic models) of your analog design for the SOC verification? As far as I kown, 1 write the models by the designer self using...
  2. L

    Verilog-A mixed signal cadence adc

    Re: Verilog-A model for ADC Thanks! I'll do some practices
  3. L

    Verilog-A mixed signal cadence adc

    Verilog-A model for ADC Dear All It is posible to get a model of ADC using Verilog(including delay from clk to outputs and an input voltage to 10 or more bits binary numbers, even filter) Why is Verilog-A usually used in modelling ADC? I am a beginner in Verilog-A. :-[ Thanks for your...
  4. L

    question about the ring oscillator

    It is impossible to be a sin wave, generally adding some inverters to make the output a square wave.
  5. L

    Is the lay out a good job?I am interested in it

    uh,My neck feels pain if doing much layout. My eyes also feel uncomfortable.It is a hard work.
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