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Recent content by lvlei0309

  1. L

    how to calculate jitter in cadence virtuso?

    Re: how to calculate jitter Can you send me a copy by the way ? lvlei0309@126.com
  2. L

    osc frequency changed in simulation !!!

    osc frequency changed!!! if u use pss run the simulation it is possible. pss sometime is not correct. i guess it is 5GHz. At some case, pss take two cycles as one , so cause 2.5GHz.
  3. L

    Choose between resistance and capacitance.

    100Nano? or pf?
  4. L

    how can i improve my PLL?

    Is your system stable?
  5. L

    3dB Bandwidth of resistive load Diff amp

    I think it is 1/(2pi(CL*(Rd+2R2))
  6. L

    way for calculating lock time of a PLL in the design process

    Re: PLL lock time [hlp] As far as I know,the setting time can be affected by the gain of PFD
  7. L

    OPAMP Buffer dimension

    this a LDO structure
  8. L

    MOSFET mismatch in the differential pairs

    Re: Mosfet Mismatch mismatch prob, u can consider it on the aspect of offset volt
  9. L

    how to simulate the gain and offset of dynamic comparator

    Re: how to simulate the gain and offset of dynamic comparato Not all comparator is positive feedback,and camparator can know the gain.
  10. L

    offset of fully differential amplifier

    Connect the OPAMP with buffer structure, can simulate the offset volt. Use montecalo analysis can track the change of offset volt.
  11. L

    PLL design with matlab Matlab

    U can just writte the transfer function in Matlab, and then smulation
  12. L

    fingers and multipliers

    I think that they are the same in schematic.But in Layout, Fingers have less parasitic cap.
  13. L

    Why is it not possible to associate poles and zeros in .lis file of HSPICE?

    Re: pole zeros in HSPICE I want to know how to find the node.
  14. L

    how to plot Vth vs Vgs in cadence

    ids vs vgs cadence Thanks for every one
  15. L

    help! How can I plot the Vth in analog design env

    plot threshold voltage with cadence Vth can directly be seen
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