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Recent content by lufeng21cn

  1. L

    Looking for good book on system verilog and tutorials

    system verilog how many verification engineers use systemverilog in verificaton-project? want this book <<writing testbench using systemverilog>> .
  2. L

    cycle and event simulation

    you can read the book <system-on-a-chip methodology an techniques!!
  3. L

    perl or tcl, which is better for eda scripting

    I think these two languages is important,because of their property.
  4. L

    What do u mean by design for verification

    like the assertion verification method,it can give you a convenient avenue to verify your design.
  5. L

    set_fix_multiple_ports_net ,what means?

    hehe,i learn some knowledge about DC,thanks alot!!
  6. L

    Need Verilog code for 1 signal for 1 period after 16 clock cycle

    verilog code(urgent) I agree with nand_gates ,maybe a counter is better!!
  7. L

    verilog coding style:IF,ELSE VS case?

    casex ({expi_sfr_cs, sec_sfr_cs, dma_sfr_cs,cmem_sfr_cs, dmem_sfr_cs}) 5'bxxxx1 : int_sfr_data_in = dmem_sfr_dout; 5'bxxx1x : int_sfr_data_in = cmem_sfr_dout; 5'bxx1xx : int_sfr_data_in = dma_sfr_dout; 5'bx1xxx : int_sfr_data_in = sec_sfr_dout; 5'b1xxxx : int_sfr_data_in = expi_sfr_dout...
  8. L

    who have some references about OUT of ORDER alorithm of CPU!

    help!! who have some references about OUT of ORDER alorithm of CPU!!
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