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Thanks a lot, your hint worked great!
I replaced
compile -ungroup_all -map_effort medium -area_effort medium
with
compile -map_effort medium -area_effort medium
ungroup nlmisr*
Then my verilog output gives me
NAND2_X1 nlmisr01_U39 ( .A1(set_ff_data_3), .A2(set_ff), .ZN(nlmisr01_n28) )...
Hi,
I am using Synopsys Design Compiler (Version B-2008.09) to create a Verilog file from a circuit specified in several VHDL files.
The top level circuit given in VHDL includes several shift registers:
entity cossma is
port(
input: in std_logic_vector(3 downto 0);
clk: in std_logic...
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