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thanks,
can you provide me with a straightforward example (in the gui or through the commandline) ?
Otherwise I will dig into the very extensive encounter docs.
Cheers,
D
Hi buddies,
I've a couple of design (final layout netlist after PNR with soc encounter)
that I want to compare from several viewpoint such as:
• power distribution
• heating distribution
• voltage drop
Do you know which software I should use in order to get a picture with
my design and the...
Hi buddies,
let me try to briefly summarize what I do before illustrating the problem.
I have a design with 16 sub-blocks.
1) the design is partitioned and 16 partitions are saved
2) I work block by block doing place and route
3) when all the blocks are placed&routed I reopen the main design...
Hi guys,
I think this is a very simple question for you but it's driving me crazy :-(
I'm synthesizing a design where I send out a negated version of the clock.
Let's assume this is a counter that has an assignment like:
assign clk_out = !clk;
of course this is translated with an inverter...
Hi guys,
I'm trying to solve a problem related to clock skewing.
I've two clocks in my design and I know I can specify to the CTS engine of SOC encounter that I want at most X picoseconds of skew tolerated for that clock. This parameter is called MaxSkew in the .cts specification file. So now...
In both cases I have violations the only difference is how big they are:
- both FF: 1.7ns
- 1 FF and 1 latch: 3ns
As far as I can see from the report_timing in prime time:
Point Incr Path
...
..
time borrowed from endpoint...
Hi guys,
I am facing the following problem since a while: blockA <--> blockB,
at the output of blockA there is a FF and a wire that goes as input to a latch
in blockB.
If I place these two blocks in soc encounter with a certain distance (5mm)
I see a certain delay (~3ns) on the link...
clock skew balancing
Hi guys,
while using SoC encounter, I didn't quite understand a couple of options
you can provide the CTS engine with:
- clkgroup (the sinks of all clock root pins listed in a ClkGroup statement
will meet the maximum skew value set in the clock tree specification file...
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