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Recent content by lucbra

  1. L

    FPGA RS232 Communication

    start with debugging your state machine, it doesn't increment to the next character, and it's just the beginning of a UART transmitter. If you've done that, you will probably know by then how to inject your input trigger.
  2. L

    Use an FPGA board for outputting parallel bits (parallel 20 bits ) at 100MSPS?

    from your own chip you will know what interface standard it expects (I hope) and DDR3 has a well defined electrical interface well above 100Mbps. Even if you don't use DDR3, Virtex7 has I/O that achieves higher bit rates then 100Mbps. BTW : A data rate of 100MSPS doesn't make any sense
  3. L

    Lattice pDS tool

    Well, to be honest ... if that particular device from Lattice is so important to you (or the company you work for), then you/they should have an image of the CD with the license file somewhere around. As posted previously - most obsolete devices are supported through the ispLEVER (I believe even...
  4. L

    An accurate seconds counter in VHDL

    how much do you want to pay for your accuracy?
  5. L

    how to read video with FPGA?

    reading the video is not the real issue. A spartan6 can do this job. You might concider looking at SoC FPGA's (Zync or Cyclone5 or similar) for the processing part.
  6. L

    [Moved] FPGA in feedback path of guitar amplifier

    Why would you only take the feedback loop in the FPGA? You can process the audio chain perfectly in the FPGA. Do you actually understand the concept of digital signal processing?
  7. L

    [SOLVED] VHDL addition "1111"+"1111"=FAIL

    Re: VHDL addition "1111"+"1111"=FAIL yes true for the second piece of code - I was referring to the original part in post #1. '+' has higher precedence than '&'
  8. L

    [SOLVED] VHDL addition "1111"+"1111"=FAIL

    why not using unsigned in stead of std_logic_vector for cnt and count?
  9. L

    counter using vhdl and implementation in fpga

    The problem is that someone might find this code using google and start using it. Isn't there a possibility to scrap this code?
  10. L

    resent areas developed in finite state machine

    Do you really think that someone will help you with this one? What have YOU done so far. The forum is not meant to do your homework/research.
  11. L

    Programming Lattice iCE40LP

    Have you asked your local Lattice representative's FAE? If they don't know it - try to contact Lattice itself. If you think that's too much trouble - go for another vendor.
  12. L

    counting consecutive zeroes in 32 bit and shifting in one cycle

    If I remember well, we had this discussion a couple of years ago ... using VHDL
  13. L

    Implementation 12 RS232/Rs485/RS422 Ports in FPGA

    and forget the idea that FPGA's (programmable logic in general) are like MCU's.
  14. L

    beamforming design for MIMO decode-and-forward relay channels

    you wish ... It is one of the main tasks of an engineer to study a problem before solving it
  15. L

    [SOLVED] What happen when use a FF triggered by falling edge of the clk?

    As you mentioned it's a homework question ... you might concider writing down your own thoughts. If it was a professional problem - I should concider a timing simulation.
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