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Recent content by lubee

  1. L

    transferring from clock domain

    in order to be safe, you can extend one cycle of the signal at the clk1 domain into two cycles and use 2 FFs to synchronize it to the clk2.
  2. L

    clock and reset design structure for SOC or Lower Power SOC

    thank you for your reply. in some cases, always-on power domain should keep their values so they should not be reset before the PLL shut down. I can gated these clock before the shut-down pll, after cpu is power up again and release them then. But this scheme needs SW to coordination.
  3. L

    clock and reset design structure for SOC or Lower Power SOC

    Hi, buddy Do you have any books or papers about the latest clock and reset logic design for the current SOC which become more and more complex and will have all kinds of power domain. For example, I came across a clock/reset problem in the real silicon: I used PLL's stable signal as some...
  4. L

    confusion about Synopsys 90nm Generic Library.

    hi, buddies, Got it!!! thanks so much.
  5. L

    confusion about Synopsys 90nm Generic Library.

    no body knows?
  6. L

    confusion about Synopsys 90nm Generic Library.

    Hi, All I have download Synopsys 90nm Generic Library which is used for education. it contains so many items, one corn lib of which (SAED_EDK90nm_ccs_models_hvt) is listed as below, The directories and files are contained in the lib of SAED_EDK90nm_ccs_models_hvt clock_gating/ isoao/...
  7. L

    FIFO Depth Calculation

    I do agree with gauravas.
  8. L

    Help me the holdtime problem

    "But how about the holdtime? when the clk=1,the first tran_cmos is turned off, why the input data d shoud be stable after the clk=1." I suppose that this is because of the propagation time that is required by the following combinational logic circuit.
  9. L

    Book for simulation tools

    refer to the following webs: www.modelsim.com and www.xilinx.com or **broken link removed**
  10. L

    modelsim running error

    hi,brother, suggest you that you should reinstall the modelsim. regards.
  11. L

    A free ict term project on transmission media

    please talk about it in details. 3Q!
  12. L

    Coding the Logic Minimization

    Logic Minimization using FSM can reduce the width of the counter, so it is a good way to reduce the logcal resources.
  13. L

    when clock and reset are on the same clock edge .

    if your reset is asynchronous, you must pay your high attentions to "recovery" and "removal" check.
  14. L

    I have an intrest to make a project in VLSI related to FPGA

    i am working on the implementation of DSP using VLSI, if you need help, please contact me via my email:lubee1@163.com
  15. L

    looking for resources on DC,3Q!

    I am a new beginner to study the synopsys DC. I know the SolvNet is a good place for study resources,but i have no so-called "active ID", So i was denied by it. would you send me some study resouces on DC,such as examples, and synthesis scripts template. Thank you in advanced!
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