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Ps, this PLL is a digital PLL, and so the higher order harmonic of the reference should be around the chip which is easily to make DCO failure for the work
Hello BigBoss,
Thanks for your feedback. I think you are wrongly understood what is my meaning.
It is a measurement results, and the circuit works well in simulation.
It means due to the 8 times harmonic of fref couples to the circuitry near the ring oscillator, and also due to the divider...
Hi,
It's a Integer PLL with N=8,
During PLL test, we find the 8th-order harmonic of the reference signal can make the oscillator itself locking at 8*fref , and the pll loop seems to have no help on the tuning of the PLL.
It's called something like "Injection and Locking or Pulling" effect, and...
Hi All,
When I design a current starved low power ring osc, I find the frequency goes up with the temperature increasing and it is quite different from my previous experiences.
After careful investigation ,I find the mosfet is working in sub-threshold region, and so it switches from...
Hi,All
I'd like to ask what is actually gnd reference for RFID Passive tag (such as 13.56MHz NFC) ?
because there is no connection to the PCB or any physical ground, how to define the ground for the reference of the internal circuits ?
Do the tags need a very solid reference ground for the...
Hello everyone
I simulated the FS using tools of spectreverilog(which can do ams simulations) ,and the output voltage of charge pump is showed as follows,
what's the reason for it ?
Thank you
error no matching .subckt statement
I mean there is a formula to the W and L from layout,and you can use it to calculate the values extracted.then compare it with your schematic value ,maybe
you find the error .also there is a error scope ,you can also correct is to run through LVS.
wish you...
hi ,all,
Recently, i have investigated many kinds of differential LNA,and sorted them in two
kinds,with the biasing isource to connect to the ground ,and without it,
so i want to know ,which kinds is better?
my design target is wideband 3-5G, gain :15db,mathing :10db
thank you in advance!
no matching subckt statement for
i think you should refer to you LVS rules,it says how to get the parameter W,L from layout!the cap should be like a squre,so W and L is nearly the same.
by the way,what process do you use in your rf design?
hi all,
i have design a LNA with 2 stages,and want use the deep nwell device to improve
the performance ,but the deep nwell device is five teminal (B,G,S,D,T) how should
i connect the T terminal in schematic and the layout?
and ,does triple well means "nwell ,pwell,and deep nwell"?
thanks in...
thank u ,I have read that book many times ,and its LNA chapter is not considering the effect of bondwire and pad ,and the working condition is ideal,but mine is not. my circuit is working on 3-5GHz, so the imput match should be wideband!
how do i make it?
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