Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I built the ADC schematic and tested a two-stage FIA structure, which can achieve an open-loop gain of 46dB and a three-stage one of 78dB, but when I added it to my pipelined sar, the voltage change of the upper and lower pole plates of the front and rear stages gave me the feedback that it did...
Hi all, I am doing pipelined sar design with FIA structure as interstage margin amplifier. However, I found that the FIA amplification is very poor when my residual signal goes to μA stage, please what is the best idea to improve the FIA
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
