Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
many thanks
i tried to connect a replicated pack array(in {2{pack_array}} manner) to an unpack array port, and also tried to connect a replicated single bit wire as in {2{single_bit_wire}} manner to an unpack array port. Neither worked.
So, is it the conclusion that any replication of...
I'm trying to connect the primary inptus to input ports of sub as
in[1][31:0] ---> sub.in[0][31:0]
in[1][31:0] ---> sub.in[1][31:0]
in[0][31:0] ---> sub.in[2][31:0]
in[0][31:0] ---> sub.in[3][31:0]
I don't think the tool accepts
sub sub (.in({in[1][31:0], in[1][31:0], in[0][31:0]...
Could someone tell me how to connect unpack arrays in system verilog in the following example ?
module sub (
input [31:0] in [0:3];
....
);
endmodule
module top (
input [31:0] in [0:1];
....
);
sub sub (.in(????????));
endmodule
Now I want to connect primary input, in[0], to in[0] and...
It will affect setup and hold of F2 only if you change the drive strength of F1 to the extent that it has much impact on rise and fall time at F2 data input.
If the logic between F1 and F2 is deep enough and has cells with reasonably good drive strengths, it doesn't make much difference in the...
If 0 state is carried over from the previous cycle, the drain remains 0 without directly being grounded at that moment.
I meant applying 0 or 1 on the source terminal.
A channel of a nMOS turns off when gate-source or gate-drain voltage becomes smaller than threshold voltage. Keep this in mind...
Imagine that you have a nMOS pass transistor where gate=0, source=1 and drain=0. Now you apply 1 on the gate which leads the nMOS to turn on and the current starts...
What I said before applies when the setup check is performed on a standalone negedge latch(if the time borrowing is allowed, setup check can be done on pos edge). A clock gating cell with a neg edge latch in it has a little different character and the setup check must be done on pos edge.
A...
a neg edge latch becomes transparent when the clock is low and you generally want the input data to settle before the latch becomes transparent(unless you allow the time borrowing). This makes the setup analysis to be done on falling edge of the clock.
A flop has the same neg edge latch as a...
PT man page says,
In bc_wc analysis mode, the -min and -max options specify the corner
for the clock latency value (fast or slow), and the -early and -late
options specify the early or late latency value within the corner. In
the on_chip_analysis mode, the...
they are essentially the same. Instruction set and microarchitecture for microprocessors are more generic and those for DSP are more optimized for signal processing. Just like a passenger car and a truck. They all have 4 wheels, an engine, a transmission, but optimized for their own purpose.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
