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Recent content by lonsta

  1. L

    verilog （ ? : ）expression to VHDL

    Thanks for such a quick reply, I got it I have to write more codes. I just performed a simple simulation and through the simulation it's clear that for verilog code above , carry and phase_acc is refreshed right when the phase_acc changed, but for my VHDL code the data refreshed one clock later...
  2. L

    verilog （ ? : ）expression to VHDL

    Hi, I am considering how to translate a verilog expression to VHDL as : {carry, phase_acc} <= (carry ? init_phase : 0) + phase_acc + phase_step; I write some vhdl code like this : ---------- phase_step : in std_logic_vector(11 downto 0); -------something something------- signal pha_acc ...
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