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Re: regd VHDL n UNISIM
Hi go4sandesh_vsn,
as far as i know, unisim lib comes from xilinx.
So whenever you want to use xilinx core in your fpga, you can use unisim lib instantiate component used in your design (as described in your fpga manual).
Then when it comes to synthesis stage, xilinx...
Hi lzh08,
it should depend on the fpga chip you are going to use.
I once used virtex II pro, and sth like that i have used:
+ using unisim library from Xilinx
-- synthesis translate_off
library unisim;
use unisim.all;
-- synthesis translate_on
+ Depend on the size of RAM required, here i used...
fpga clock connect pin
Hi Salma,
I think you can use DCM in FPGA to get clock with different frequency from the input global clock. DCM can generate "good" clocks for you.
Hope it helps.
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