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Recent content by Loktik_Vitalij

  1. Loktik_Vitalij

    Calibre DRC/LVS student guide and lab

    calibre LVS/DRC workshop
  2. Loktik_Vitalij

    How to draw multipath with user input netnames in Skill ?

    rodcreatepath multipath hiSetBindKey("Layout" "F8" "line()") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;enterpath;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; procedure(line() let((path_width path_space path_number path_point width cvId layer purpose list_draw_layer)...
  3. Loktik_Vitalij

    Looking for a more advanced Cadence tutorial

    Virtuoso Advanced Analysis Tools User Guide noise and corner gm/id **broken link removed**
  4. Loktik_Vitalij

    cadence ic design sofware request

    cadence ic design ic6. This SOFT is not freeware
  5. Loktik_Vitalij

    can I can include 2 statement inside if condition in Verilog

    VerilogA in Analog maybe if ( a == 0 and b == 0) or if (( a == 0) && (b == 0))
  6. Loktik_Vitalij

    About the definition of MOSFET's threshold current

    threshold mosfet definition calculated threshold current
  7. Loktik_Vitalij

    reduce subtate resistance in Layout

    subtate resistance use row(s) a contact for connection to gnd
  8. Loktik_Vitalij

    how to change the Virtuoso's black background to white ?

    Re: Virtuoso background use WaveScan (not AWD).
  9. Loktik_Vitalij

    corner simulation in Spectre

    simulation with 32 corners cadence example
  10. Loktik_Vitalij

    What is the minimun channel length for a CMOS transistor

    >>ok, is Lmin= 0.35um and using the lambda rule, Lmin=2Lambda => Lambda=0.35um/2 that would be correct, right ?. this is correct >>The thing is i design a circuit who has all the transistor using the minimun length, why because is for high frequency operation. for the minimum length of channel...
  11. Loktik_Vitalij

    Help with plot in cadence

    Message is unavailable.
  12. Loktik_Vitalij

    need your help (technical Analog layout)

    1. C Mask Design: Essential Layout Techniques by Christopher Saint, Judy Saint 2. IC Layout Basics : A Practical Guide by Christopher Saint Judy Saint 3. The Art of Analog Layout by Alan Hastings, Roy Alan Hastings 4. Direct Transistor-Level Layout for Digital Blocks by Prakash...
  13. Loktik_Vitalij

    Virtuoso Compactor Reference Manual

    in the Cadence Documentation folder: compactref.pdf or **broken link removed** | 1087 KB
  14. Loktik_Vitalij

    Why does vth vary with length?

    Re: vth vs Length Eq (1) states that the threshold voltage is only a function of the manufacturing technology and the applied body bias VSB. The threshold can therefore be considered as a constant over all NMOS (PMOS) transistors in a design. As the device dimensions are reduced, this model...
  15. Loktik_Vitalij

    Who use Cadence 610 ? ?

    cadence version 6.1.2 ads >>So, far, I have not seen any PDK released for Cadence 610 (except Cadence GPDK). tsmc0.18->cdb2oa. While only so.
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