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Recent content by loka99c

  1. L

    How to verify whether the RAM model is correct?

    hi, In my design the verilog model of RAM. This model is only a behavior model and it aims to make the design functionally work. For synthesis, another ram model is used to replace this verilog model. The problem I'm facing is how to verify whether the synthesis ram model (real ram code) has...
  2. L

    [DC] What does the "default group" mean in DC timing report?

    Thanks vijay. :-P Then can the violations in this group be ignored, or should I fix them? And what would cause DC not able to further improve the paths?
  3. L

    [DC] What does the "default group" mean in DC timing report?

    Hi, anyone knows what does the "default group" mean in DC timing report? (End-point violation report). Why this group isn't belong to any clock group?
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