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Recent content by lohi21

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    it is empty in the Cells List while Generate Clock Spec

    1. Check if you have included the physical views of the buffers/inverters (LEF view) 2. check if the functionality definition defined in .libs 3. Check for the log file, (Normally while loading the design, Encounter would specify the list of usable buffers/inverters). If not,it should give out...
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    To create .lib model file a macro

    Hi mit1986, Assuming that the macro has been completed (routed) and need .libs for STA environment setup. man do_extract_model in EDI environment, and it will list out the options / switches for generating the .libs from the PNR environment. normally, .libs will be generated from the PT/ ETS...
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    What is testchip and why we need them ?

    mr_vasanth, Test chips are normally be done for the verification of IP's on die, or checking for new technology or even it could be to check the behavior of the IP with the different technology on die. All aspects of chip design is the same for test chips and production chips. but can see...
  4. L

    Difference between Via and Cut??

    yes, ur right on certain terms.
  5. L

    bringing block level sdc to top level

    Has the 2 blocks PNR completed? If yes, Has the ETM models generated by the PT/sign off tool? If done, then most of the information is available at the .lib's of your blocks and write out correct SDC at the top level by giving correct number for set_input_delay and so.. This would generated...
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    Number of ground pads used in a design

    Hi sputty6, The attachments will give you more information of multiple P/G pads in the design. Hope this helps.
  7. L

    DC synthesis Unconnected input

    DC does not automatically tie inputs or outputs. you will have to either get that info from RTL or use command to tie unconnected pins.
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    Synopsis ICC and Design compiler

    I am not sure if the videos are available, But try googling for ASIC design using synopsys tools. Attached is the basic one.
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    Floorplanning , Timing optimisation and Power optimisation methods in IC Compiler

    Start with the tutorial, Some one in your company might have atteneded the IC compiler workshop. Go over the book and try to familirise the flow first. all PNR tool would differ while implemention. Which ever tool you have been assigned, start with workshop of that tool first, get familiarized...
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    Place and route on flat full chip

    All entities of PD remains the same for the block level and chip level, except that you you will floorplan the design considering the package, (Wirebond or flip chip). Power planning, this time you will have to come up with the total power consumption by the chip and plan accordingly. just run...
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    PERL: Plz suggest a textbook/pdf/tutorial..

    If the learning is intended to automate the EDA flow, I suggest you see the video @ solvnet. It would be good start.
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    Command for finding the coordinates of a macro in Encounter

    select all the macros and then reportSelected will give u coordinates, orientation and other info. Grep for instance name and its location co ordinates. As yada VLSI script does the work, and i recommend you gain expertise over the db commands of Encounter. It will help when the database is huge.
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    setting of captables for different corners

    Plz interchange max corner -> worst case min corner -> best case - - - Updated - - - Plz interchange max corner -> worst case min corner -> best case
  14. L

    Number of ground pads used in a design

    To have better sinking advantage. and to reduce the path completion resistance, else u might have end up having huge ground bounce

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