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It's exactly the same design...The inputs and logic power dissipation in V2 are the ones greater than in virtex4..
And it's virtex2pro if this makes any difference...
I used power analyzer after place and route... and virtex2 pro keeps giving less Pd :S for the exact same design..
Added after 1 minutes:
rca,
what you mean is not clear..
V2 works on 1.5V
V5 works on 1.2V
They both have an auxillary voltage of 2.5 though,
Would you be kind enough to explain to be if this sytem would work at 5.1ns or the 1.9ns the report claims to have achieved??
OFFSET = IN 1.45 ns VALID 1.9 ns BEFORE COMP "clk" HIGH;
Worst Case Data Window 5.099; Ideal Clock Offset To Actual Clock 1.144;
Design statistics:
Minimum period...
Very clear illustration, thanx : )
One more question, in the later example you gave, does this mean the maximum freq. for correct operation would be 0.9ns?? i.e. generally is fmax= s+h??
I have no constraints what so ever set for my design but the static report has some positive and negative values for the setup to clk and clk to hold..What is the indication of these values and what's the difference betweenthem being + or -???
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