Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Thanks so much for the help! Yes a mux seems like it would be great. So something like this?...
...
input [2:0] key;
...
case(key)
0: adder(most, least, result);
1: subtracter(most, least, result);
2: multiplier(most, least, result);
endcase
I'm just not sure with how to...
So I've been working on this project for class...
Using Verilog, design an adder-subractor-multiplier circuit that will perform these operations on 2
3-bit numbers as follows,
Use SWO-SW2 to represent the first 3-bit number (least significant). This digit will be
displayed on 7-segment...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
