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Recent content by ljp2706

  1. L

    Need suggestions for over voltage protection

    Does anyone have suggestions for an over voltage protection circuit? I have a signal that slews very fast, where a comparator will not be quick enough to react. The only ideas I could come up with were a clamp structure or a series MOSFET with the gate biased to saturate the signal but that...
  2. L

    pnoise/pss question

    Thanks for the input. I did what you said and I was able to get pss to converge on the proper solution. The issue I am seeing now is that the noise plot is much higher than what I expected and does not match up to the normal noise analysis. One thing that helped was not sweeping frequency to a...
  3. L

    pnoise/pss question

    I have a design that is an autonomous frequency circuit. For it to initialize properly in the transient domain analysis I have a dynamic parameter set to force a reset. So technically I don’t have any driven frequency sources in my schematic. I am having trouble getting pss to show the correct...
  4. L

    Current-starved Inverter as delay element.

    What is your supervisor suggesting you use them? This is one of the more common architectures I’ve seen anyways. The one thing to watch here is going from the “slow zone” back to the “fast zone”. If you’re going for a very slow delay think milliseconds, you will have a lot of contention on M8/M7...
  5. L

    cadence layout metal width (in high current, in long wire)

    For long wires that carry significant current thickness is usually not limited by electromigration. You need to assess what the maximum tolerable IR drop is on the line and then size the width to be less than that. I like to do a parametric sweep of resistance on the supply and monitor some key...
  6. L

    Help finding a digital counter architecture

    Thanks for the fast response! I tried this architecture and it didn’t work for me because the leakage at the charge storage nodes was too significant. For the MSB, I have to hold it for more than 30ms. I took a look at a bunch of other dynamic architectures, there is a great paper out there on...
  7. L

    Help finding a digital counter architecture

    Is it possible to make a digital ripple counter out of 6T SRAM cells? I’m trying to make the most area compact architecture I can find. I need to have asynchronous reset capabilities and the ability to latch each output value without interfering with counting. Right now the best I can do is a...
  8. L

    Deep nwell connection

    Deep nwell just provides a well to put p-implant. And the most important thing to consider is that the p well to dn well never forward biases. That is usually done by reverse biasing to the highest supply. The PMOS devices in the n-well usually are not in the deep nwell. If they are, then you’re...
  9. L

    Deep nwell connection

    I agree. Unless you have hundreds of wells, you’re not going to save a lot of space by combining just three. There’s less risk with keeping them separate.
  10. L

    MOSFET Speed and power tradeoff

    Just to clarify something, strong inversion is not the same as saturation. Strong inversion is the point where you have significantly overcome the surface potential and have created an inversion channel between the drain/source. The gate voltage applied is what creates this channel—that is why...
  11. L

    DRC and LVS in Calibre

    Are you having difficulty understanding the actual violation, or using the tool? If you’re having a hard time understanding the violations, the PDK documentation usually includes a DRC manual that has a more detailed explanation of the violations. I would suggest trying to find that document to...
  12. L

    Deep nwell connection

    Provided that you reverse bias the deep nwell to the highest of the three supplies, you can share the deep nwell. Just make sure you follow any violations/considerations implemented by the DRC rule deck/PDK. The three different grounds would each have their own ground biased pwells within the...
  13. L

    Why we should choose even number of finger

    I think it’s primarily done for layout matching. As long as your schematic is readable, doesn’t violate pdk requirements, meets specifications, and matches your layout, it doesn’t matter too much what you do with your devices from a schematic point of view. Ultimately the layout is what gets...
  14. L

    "calibre view generation encountered a fatal error" but spectre PEX extraction works

    Re: "calibre view generation encountered a fatal error" but spectre PEX extraction wo What are the simulation errors? Also, what does the CIW say after the file is generated?
  15. L

    Why we should choose even number of finger

    Even numbers of fingers are better because it makes the device layout symmetric. You have two sources and one shared diffusion. In the case of a source coupled differential pair, since the sources are common, you can share source diffusions of device A with device B. Something that isn’t easily...

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