Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi All,
I am working on digital PLL which include VCO, frequency divider, TDC, digital filter. I want to simulate the digital PLL in cadence. I have the transistor level implementation of all blocks including digital filter. If i include digital filter in the simulation using transistor level...
I would like to do a down sampling in my ADS transient simulation. I found on the internet there is a component "DSampleRF" on the web.
http://edocs.soco.agilent.com/display/ads2009/DSampleRF
How can i get this component?
how to design simple combinational circuit 6 bit by 6 bit unsigned number divider using modules such as adders?
I know multipliers can be constructed using adder arrays. how about dividers?
I want to implement a simple PI digital controller for DC-DC converter. Should i choose unsigned or 2's complement number representation?
for unsigned, unsigned numbers can not represent negative numbers. for 2's complement, the following ADC is accepting unsigned numbers.
Hi yadavvlsi,
Thanks for your reply! i understand it does not occur in normal operating condition. But in CMOS RF VCO design, the transistors are potentially stressed. That is why I want to know the breakdown voltage between drain and body.
Hi Preetam,
Thanks a lot for your reply! The 4 bit adder is a pure combinational circuit. It seems that the VHDL code make a sequential circuit of 16 bit adder which consists of the combinational 4 bit adder, registers and clocks. And the input to output delay should be 2 clock cycles if i am...
HI, all
i want to make a 16 bits full adder circuits. I have read some paper and most of them talk how to minimize delay and power of a single bit fully adder cell. Should i cascade 16 1 bit full adder circuit to make my 16 bits full adder circuits? if so, the carry bit delay will be 16 times of...
Hi biff44,
thanks for your reply!
i agree that phase noise goes up by 3 dB. But when we convert from phase noise to jitter, we have to divide phase noise by 2*pi*fc. So phase noise goes up by 3dB, but center frequency also go up 2 times.
assume that the two input to the mixer are of same frequency and same phase noise, the output frequency will double. what is the relationship between output frequency jitter and input jitter?
are they the same?
Hi,
As you mentioned, there are 3 resistors in series for the 1 bit case. So there will be 2 comparators. As the input voltage goes from low to high, the 2 comparator output should be thermal code starting from 00 to 01 and finally 11. Next the thermal code need to be converted to binay code...
In the one bit case, the output thermal code will be 00, 01, 11. How should i translate this to binary code of 0 and 1? 00 correspond to 0? bot 01 and 11 correspon to 1?
for the simple flash ADC， the voltage reference for each comparator is generated by injecting a current into a series of resistors. suppose one LSB is R*I. The bottom resistor should be of value R or R/2?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
