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problem:
i treat the cell and nets names as case insensitive during output my design in DC, but there still 6 nets with case sensitive problem(N42 , n42 exist in the same module),
but when i do P&R in SOCEncounter i find that SOCEncounter treats cell name as case_insensitive, but nets name...
auverilogtocell
after perform the auVerilogToCell, all the lib cells will appear in the cell list,but the command will always not sucessful ;
when i use the read verilog command,all the lib cells will appear in the cell list and the top module cell will also appear in the cell list ,but when...
back-annotation issue
by XRC .spef file is stream out
by PT .spef is read in and the sdf file is created
and the modelsim can read the sdf file in to the .v file
thus complete the back simulate of the design
setup and hold time questions
hi
for the first one , i think b is the correct answer
as the time from d to q is quite enough for it to hold
there is no need to hold
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