Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Dear all,
When I get my chip fabricated by some foundry(e.g. tsmc), what factors will affect the cost of a wafer (how much money I have to pay)?
Wafer Size(300mm/450mm)? Number of metal layers? Technology node(.18/.13)? and what else?
Is there any method to estimate this thing...
area of NAND2X1?
Hi all,
I would like to estimate the area of a circuit using the following formula:
"Area = gate count * area of NAND2X1"
But I only know the values of 90nm/.13/.18 tech(tsmc).
Is there anyone can tell me what's the area of .25/.35/65nm tech?
Thanks!
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.