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I have a simulator and a synthesize tool which have conflicting results in the following code / case:
lessthan = ((B << 1) <= B_t'(-N));
lessthan is "logic"
N is "logic [11:0]" and has value 53;
B is "logic signed [18:0]" and has value -26;
B_t is a typedef for "logic signed [18:0]";
The...
Hello,
I have a module that uses a function in the combinational logic always block. (How) Can I inspect the internal signals (or variables) of a function in ModelSim?
I have an simplified example of what I intend to do:
function logic inverse(logic x);
logic y;
y = x?0:1;
return y...
Dave,
thank you for your response.
But if there is a non-cyclic directional graph of dependencies between those constants, the synthesis tools should be able to neatly synthesize this?
So it is a synthesis tool problem, and for the next few years, we cannot use const usefully.
The nice...
Hello,
I would like to use constants in my SystemVerilog design for synthesis, which allow me to define values with a bit of arithmetic like this:
const mytype_t R = (M + (N << 1)) / (1 + (N << 1)) + 1;
const mytype_t RF = (R + 2**5) / 2**6;
const mytype_t RF = RF > 2? RF: 2;
However, I...
Hello all,
Suppose I have the following in SystemVerilog (intended to synthesize).
typedef packed struct begin
logic a;
logic b;
end mytype_t;
mytype_t myarray [1:100];
Is it possible to set field 'a' of all array members with a single assignment?
I understood from studying SV books it...
In Quartus, how can I determine the timing of the critical path of combinational logic, when I am still in the module design phase?
I get no Fmax report, I think because in this particular module I have no feedback from state registers to the combinational logic.
inputs=>combinational...
Hello,
in the example below, does the blocking assignment "y = a ^ b" also block the " q <= y" assignment until y is assigned?
module nbex1 (q, a, b, clk, rst_n);
output q;
input clk, rst_n;
input a, b;
reg q, y;
always @(a or b)
y = a ^ b;
always @(posedge clk or negedge...
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