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Recent content by leyuanniao

  1. L

    What is wrong with my simple code?

    All registers need be reset before working.
  2. L

    Help: ISE with ModelSim simulation issue

    modelsim bug asynchrone I think it's necessary using a reset synchronizer circuit for asynchronous reset. And I see a solusition suggestiong for Virtex. **broken link removed** "Xilinx recommends that the RST signal be synchronized in the ISERDES or OSERDES CLK or CLKDIV domain to avoid any...
  3. L

    Primetime workshop 2001

    prime time workshop I have the prime time workshop in 2001. Has anyone the newer version?
  4. L

    synopsys design compiler workshop

    Re: primetime workshop lab Really? It seems that I haven't make full use of the solvnet.
  5. L

    How to convert VHDL code to Verilog?

    Re: VHDL TO VERILOG Yes, X-hdl is a good tool for translating between VHDL and Verilog. I have used it to translate many codes and it works well.
  6. L

    Suggest me the best TCL book (available in India)

    i need one tcl book There is tcl introduction in Synopsys SOLD also.
  7. L

    Low-power design lessons and reference

    Low-power design I just learn a low power lesson from Infineon, which use Synopsys Powercompiler tools.
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