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It is well known there is a doublet existing in Gain boosted amplifier (Fig.1). According to the original paper, "A fast settling CMOS op amp for SC circuits with 90-dB DC gain". The zero is located near the unity gain frequency of addition amplifier, which is not hard to understand. However...
you can get ro by simulating a single transistor which is biased at right voltages. Since ro is prportionally to L^2/Vds,sat^2, normally, you can change the length of the mosfet and keep the inversion level fixed.
since vref=2.5V, then all 1s should be at vp-p=2.5V. 3Vp-p maybe means the adc still can work properly at 3V, while if it exceeds 6.5V, Vgs maybe exceed its limits.
That is what I guess. Hope it helps.
usually we use minimum length along the signal path of the circuit if really needs high speed. Except for input diff pair because matching is crucial there.
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