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Recent content by leongch

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    How to write .SPEF from DC-Topographical and read by PT

    Hello, I am trying to perform trial by using the DCT (DC topographical) vs the norma DC flow. I have problem with DCT timing clean but PT has timing violation. I guess it is something related to the RC calculation where the DCT has the DEF information but PT is purely dependent on the...
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    fsdb version convertion

    Hi, I am using the synosys PTPX 2010 to generate the power waveform (fsbd) file but it is in latest 4.2 version. But my viewer tool Cosmoscope (2007 version) can only support up to version4.1. Anyway I can downconvert the fsdb from version 4.2 to 4.1 or wise versa? Thanks
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    What's the tool QuartusII equivalent to Chipscope in Xilinx?

    Hi I am Xilinx player for a long time, now gonna fpga prototyping on altera board. Want to know what's the tool name in QuartusII which equivalent to Chipscope in Xilinx. Thanks.
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    anyone provide fpga service?

    yes ? what kinda project u are working on ?
  5. L

    Convert LinkList in C to HANDEL-C

    Hi, The handel C itself don't have this link list construct, anybody have ideas on how to implement the link list in handelC ?
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    Galois Field Multiplier for Reed Solomon Code

    Hi Thanks for reply, I am asking, how to achieve it. Like the function assign z[0] = b[0]&a[0]^b[1]&a[7]^b[2]&a[6]^b[3]&a[5]^b[4]&a[4]^b[5]&a[3]^b[5]&a[7]^b[6]&a[2]^b[6]&a[6]^b[6]&a[7]^b[7]&a[1]^b[7]&a[5]^b[7]&a[6]^b[7]&a[7]; Why is this function?? How to get into this function?
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    Solve the logic functionofgiven inputs and output

    Solve the function B 001 010 100 011 110 111 101 A 001 001 010 100 011 110 111 101 010 010 100 011 110 111 101 001 100 100 011 110 111 101 001 010 011 011 110 111 101 001 010 100 110 110 111 101 001 010 100 011 111 111 101 001 010 100 011 110 101 101 001 010 100 011 110 111 Hi...
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    Galois Field Multiplier for Reed Solomon Code

    Hi guys, I am implementing ReedSolomon Code(256,191) with 8bits per symbol I found some of the online code for Galois Field Multiplier 256 as followed. Who can tell me how to come out with this kind of XOR ? module gf256mult(a, b, z); input [7:0] a; input [7:0] b; output [7:0] z; assign z[0]...
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    galois field multiplier - help with XORing

    galois multiplier Hi guys, I am implementing ReedSolomon Code(256,191) with 8bits per symbol I found some of the online code for Galois Field Multiplier 256 as followed. Who can tell me how to come out with this kind of XOR ? module gf256mult(a, b, z); input [7:0] a; input [7:0] b...
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    can code coverage done on the gate level netlist?

    fault coverage netlist Hi all, I am just wondering, do we need to run the code coverage at the gate-level netlist? Can the code coverage from cadence support code coverage at the gate-level netlist? Thanks
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    VHDL to VERILOG CONVERTION

    conv_std_logic_vector verilog Hi Guys, I need to convert this VHDL code into the Verilog. I tried it with the online free converter software, the end result still have errors, can please advice over here? VHDL CODE as followed library IEEE; use IEEE.std_logic_1164.all; use...
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    combine test cases for code coverage in ncverilog

    Hi, I know how to perform single test case ncverilog code coverage, but now I am required to perform test coverage for 100 available test cases files. Anyone know how to do it?
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    Information on the DDR2 and DDR3 design and features

    For the DDR2 and DDR3, there are 1. ODT (On die termination) 2. TDQS (Termination Data Q strobe) Actually, what's the reason of these Termination is needed? Use on what time ? Also the ODT pin is for what purpose? In DDR3, there's this BC# option where we only read out the highbytes of DQ...
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    How to distinguish behavioral and structural in Verilog In

    behavioral structural verilog If it is netlist, it should be structural
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    Designing a synchronous FIFO with the registered data_out but without 1 clock cycle

    Hi guys, A ) In normal syn FIFO design, the data out is not registered. assign data_out = MEM[RD_PTR]; B) If we would like to register the data_out as always @(posedge clk) data_out <= MEM[RD_PTR]; Compared the method, the B (registered data_out) will read out the data_out 1 clk...
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