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Recent content by lengkeng

  1. L

    design compiler symbol library

    Hi, The symbol library (*.sdb) can not affect to the synthesis of Design Compiler tool. Can you show the TCL script to synthesize your design? Maybe, you setup the values of link_library or search_path variables incorrect!!! Regards
  2. L

    Re: Problems with DesignCompiler/PrimeTime Flow

    Re: Problems with DesignCompiler/PrimeTime Flow Hi, I think you setup the SDF file error, you can try one of the following ways in turn: 1. Only read the netlist (not read the SDF) file, and make the simulation ==> any error? 2. Modify the SDF file (only include delay of one 1 cell), and make...
  3. L

    Clock input capacitance - discrepancy

    Hi, Can you show more detail about your design? - may be digital design? - I measure the input capacitance on the clock pin by simulation I am getting 1.58fF ==> by which tool? - 0.6fF and 0.4fF ==> which tool? If this is the digital design, you can use PrimeTime tool to get the net that...
  4. L

    Re: Problems with DesignCompiler/PrimeTime Flow

    Re: Problems with DesignCompiler/PrimeTime Flow Hi Thawra-Kadeed, With the violation $hold( posedge CK:16 ns, negedge E:16 ns, 1 ns ), I think you got the issue when loading the sdf file. Why? Because with the timing simulation, we will never get the timing value is the integer number (16ns)...
  5. L

    DFT implementation and verification

    Hi preethi19, DFT implementation - To implement DFT for digital design, the DFT compiler (Synopsys) will replace the normal registers by the scan registers (the regiter with 2 inputs: D and TI). Then, DFT compiler will create scan chains from all registers, to control the value of all output...
  6. L

    Re: Problems with DesignCompiler/PrimeTime Flow

    Re: Problems with DesignCompiler/PrimeTime Flow Hi Thawra-Kadeed, You can use the Synopsys Design Flow to estimate the power of your design, as following: 1. Use Design Compiler to generate netlist ==> A.v, A.sdc 2. Use IC Compiler to layout the design A.v, A.sdc ==> B.v, B.sdf, B.sbpf 3...
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